Photonic integrated circuits (PICs) may be formed in a single chip or may include two or more optical chips when it is difficult or inconvenient to form all desired optical components of the circuit in a same material system. For example Silicon on Isolator Insulator (SOI) technology enables to form optical circuits including a variety of passive and active optical elements, such as optical waveguides, splitters, combiners, filters, wavelength multiplexers and demultiplexer, modulators, resonators, and the like, in a single SOI chip. However silicon (Si) substrates are poorly suited for fabricating light sources such as laser or light emitting diodes, which typically require compound semiconductor systems such as Gallium Arsenide (GaAs) or Indium Phosphide (InP) based. Thus a PIC that includes both light-generating elements and light processing elements may typically be a hybrid circuit wherein a laser or LED chip is optically and mechanically coupled to a SOI chip or the like containing light processing circuitry.
Multi-chip PICs require a continuous optical path between the chips. Optical waveguides of two optically adjacent chips in a multi-chip PIC must be aligned at a chip interface so that the optical loss is minimized and the integrity and quality of the optical signal can be preserved. That typically requires a high precision three-axis mechanical manipulation of the chips. The position of one chip with respect to another may be described using an (x,y,z) Cartesian coordinate system wherein the x- and y-axes are typically assumed to be directed in the plane of the substrate of one of the chips, which may be referred to as the carrier, and the z-axis is directed in a direction normal to the main plane of the carrier substrate, which may also be referred to as the vertical direction.
The fabrication and packaging of very small dimension waveguide structures, often based on two or more material systems and different semiconductor chips, must be accomplished with high precision along an optical reference line that requires precision alignment linear along the three axes and with respect to three angles of rotation about these axes. The final alignment must be performed in a low cost manufacturable manner, then be fixed so that the alignment does not change with environment conditions and over the lifetime of the module or subassembly. These linear and rotational alignments occur during the assembly process where a pair of chips or a multiplicity of chips are aligned to each other, and then assembled either to each other, or assembled to an additional chip or substrate, maintaining their alignment to each other.
Modern semiconductor precision placement equipment is typically much better suited for accurate micron- and sub-micron alignment of chips in the (x,y) plane of the substrate, than in the z-direction that is vertical to the substrate plane. While accurate sub-micron alignments on two of the three axes, x and y, is normally within the rapid assembly times and capabilities of modern semiconductor precision positioning equipment, the end-to end alignment of two planar waveguides in the vertical (z) direction is typically more difficult due to the lack of z-axis fiduciaries and alignment tools. The vertical alignment for the end-to-end optical transfer may also be very sensitive to tolerance buildups that may occur when assembling multiple chips.
In order to overcome these difficulties and accommodate the variation in thickness and tolerance buildup in a direction orthogonal to the waveguide's broad flat surface, active alignment techniques may be employed, which include launching light into an optical waveguide of one of the chips and measuring light transferred into the second chip while adjusting the relative positioning and orientation of the chips so as to maximize the light transfer between the chips. Although the active alignment techniques, when used, may provide desired accuracy of optical alignment between chips, it may be inconvenient to use, and generally increases the cost, time and complexity of assembling multi-chip modules and subassemblies.
There is a need for improved methods of optical alignment of semiconductor chips in multi-chip optical devices and circuits, and for optically aligned multi-chip photonic integrated circuit devices that are easier to assemble and align.